Semiconductor electrode having improved grain structure and oxide growth properties

ABSTRACT

The use of nitrogen doped amorphous silicon as an electrode material for a semiconductor integrated circuit is described. A preferred embodiment is a single transistor flash EPROM cell is disclosed having a tunnel dielectric (202), a floating gate (206), an intergate dielectric having three layers (208, 210, 212), and a control gate (218). The floating gate (206) is composed of in-situ nitrogen doped amorphous silicon. Due to the nitrogen doping the floating gate (206) retains its microcrystalline structure under high temperatures, eliminating large grain boundaries in the floating gate (206). As a result, arrays composed of the disclosed EPROM cell have improved memory cell threshold (V TM ) distributions. In addition, silicon oxide grown from the the floating gate (206) has fewer stress induced defects reducing leakage paths that contribute to data retention errors. 
     An alternate embodiment uses nitrogen doped amorphous silicon as the capacitor plates (304 and 306) in a DRAM cell (300). The nitrogen doped amorphous silicon oxidizes at a slower rate than undoped amorphous silicon and has less inherent stress resulting in thinner a capacitor dielectric (308) of fewer defects. The capacitor plates (304 and 306) maintain their microcrystalline structure throughout subsequent temperature cycling resulting in increased capacitor area.

TECHNICAL FIELD

The present invention relates generally to integrated circuits, and moreparticularly to electrodes fabricated from thin films semiconductorlayers.

BACKGROUND OF THE INVENTION

Semiconductor materials, such as patterned polysilicon, are commonlyused as electrodes in integrated circuits. Among the many types ofstructures categorized as "electrodes" are transistor gates andcapacitor plates. It is well known in the art to deposit and pattern alayer of polysilicon and then oxidize the resulting polysiliconstructures to grow a layer of silicon dioxide. The quality and thicknessof silicon dioxide grown on polysilicon can play an important role inthe reliability and performance of an integrated circuit device. Twoparticular types of devices where this type of silicon dioxide plays acritical role are dynamic random access memory (DRAM) cells andnonvolatile memory devices employing "floating" gates.

Among the types of nonvolatile memory devices are erasable programmableread only memories (EPROMs). Within the group of EPROMs are "flash"EPROMs and "conventional" EPROMs (referred to herein as EEPROMs). UnlikeEEPROMs which use Fowler-Nordheim tunneling for programming and erasinga floating gate, flash EPROMs use hot-electron injection to program andFowler-Nordheim tunneling for erase.

While many different types of flash EPROM cells exist in the prior art,the single transistor flash EPROM cell (1-T cell) has become moreprevalent due to its greater packing density. A prior art 1-T cell isset forth in FIG. 1 and designated by the general reference character10. The 1-T cell 10 includes a substrate 12 having a channel 14, asource diffusion 16, and a drain diffusion 18. A tunnel oxide 20separates the substrate 12 from a gate stack 22. The gate stack 22 iscomposed of a floating gate 24 an intergate dielectric 26, and a controlgate 28.

During programming, the source 16 is grounded, and a positive voltage isapplied to the control gate 28 with respect to the drain 18. Electronsare injected into the floating gate resulting in an overall highermemory cell threshold voltage (V_(TM)). During erase, a positive voltageis applied to the source 16 with respect to the control gate 28, andelectrons tunnel from the floating gate 24 to the source 16.

The fabrication of 1-T cells begins with the growth or deposition of thetunnel oxide 20. A layer of polysilicon is deposited over the tunneloxide 20 to form a floating gate layer. The conductivity of the floatinggate layer can be increased by in-situ doping or ion implantation. Theinterpoly dielectric 26 is then created on top of the floating gate 24.As shown in FIG. 1, the interpoly dielectric 26 is typically a threelayer dielectric of silicon dioxide, silicon nitride, and silicondioxide. It is common to form the first layer by oxidizing thepolysilicon floating gate layer. A control gate layer is formed bydepositing a second layer of polysilicon over the interpoly dielectric,and doping it, if required. The three layers (floating gate, interpolydielectric, and control gate) are then patterned to create a number ofgate stacks 22. The polycrystalline structure of the polysilicon gates(24 and 28) are shown in exaggerated form in FIG. 1. The gate stack 22is subject to a subsequent oxidation step to form oxide sidewalls. Theremainder of the fabrication process continues using well know steps(the so called "back-end" of the process). The back-end can include anumber of additional temperature cycles.

Despite the advantages of flash EPROM technology, a number ofreliability issues exist in the prior art. In flash EPROM memory designsa number of cells share a common source node allowing for thesimultaneous (flash) erase of the entire memory array or a portionthereof (also referred to as a "sector" or a "block"). One problemraised by this erase function is that of "over-erase". In the event acell possesses an erase (tunneling) current greater than the other cellsin the array (or sector), during a given erase operation the cell havingthe higher erase current will be over-erased while the other cells areproperly erased. Over-erase results in unacceptably low V_(TM) and canresult in the cell functioning as a depletion mode device. An aspect ofthe over-erase mechanism for floating gates of polysilicon constructionis discussed in IEEE Technical Digest IEDM 1994, pp. 847-850 in anarticle entitled "The Solution of Over-Erase Problem Controlling Poly-SiGrain Size--Modified Scaling Principles for FLASH Memory" by Muramatsuet al. The article demonstrates how "oxide valleys" can occur at grainboundaries, and as a result, larger grain floating gates present largerdistributions in V_(TM).

A number of methods addressing the over-erase problem are set forth inProceedings of the IEEE, Vol. 81, No. 5, May 1993 in an article entitled"Reliability Issued of Flash Memory Cells" by Aritome et al. The methodsset forth in Aritome et al. have drawbacks however. The use of a seriesenhancement transistor adds to process complexity, and increases overallcell size. The various verify-erase methods can require additionalcircuits and can increase erase time substantially.

A second reliability issue discussed in Aritome et al. is that of dataretention. After a cell has been programmed, various mechanisms,including oxide defects can lead to the electrons leaking from thefloating gate. Leakage paths can occur through the interpoly dielectricto the control gate, or through the tunnel oxide to the substrate aswell. Data retention failures cause low V_(TM) in programmed cells. Asevere enough data retention problem results in programmed cells havingV_(Tm) s that approach those of erased cells.

Commonly-owned, U.S. Pat. No. 5,416,738 entitled SINGLE TRANSISTOR FLASHEPROM CELL AND METHOD OF OPERATION, incorporated by reference herein,discloses a flash EPROM arrangement wherein a negative voltage isapplied to non-selected cells during read operations to tolerate a widerrange of erased (and even over-erased) cell V_(TM) s.

While the interpoly dielectric of flash EPROM cells can play animportant role in the reliability of the flash devices, a similarstructure also plays an important part in DRAM cells. It is known in theprior art to fabricate DRAM cells having a cell capacitor formed by asandwich layer of a first layer of polysilicon, a capacitor dielectricand a second layer of polysilicon. To increase the sensed DRAM cellsignal, various methods have been introduced to increase the capacitanceof the cell capacitor. Such approaches have addressed three variables ofcell design; increasing capacitor area, using dielectrics having higherdielectric constants, and reducing the dielectric thickness. Forexample, it is known to increase capacitor area by depositing a"textured" layers of polysilicon. To increase dielectric permittivity itis known to use higher dielectic constant materials such as oxy-nitrideor tantalum oxide. Reducing the dielectric thickness requires attentionto properties such as the polysilicon interface and grain size whichchange as a function of growth and back-end temperature cycles. Thegrain structure affects the quality of the dielectric (such as itsleakage properties, as described above).

In a field unrelated to floating gate technology, an improved localoxidation of silicon (LOCOS) technique is presented that utilizesnitrogen-doped amorphous silicon to reduce the stress and formation ofvoids during LOCOS in IEEE Technical Digest IEDM 1994, pp. 683-686 in anarticle entitled "Nitrogen in-situ doped Poly Buffered LOCOS: Simple andScalable Isolation Technology for Deep Submicron Silicon Devices" byKobayashi et al.

While those references directed to flash EPROMs provide many solutionsto the over-erase problem, arrays of 1-T flash cells continue to bemanufactured with V_(TM) distributions that are either too wide tocompensate for with the prior art methods, or, if correctable by priorart methods, would introduce additional process complexity or anunacceptable amount of additional circuitry. It is therefore desirableto provide an EPROM cell design that results in tighter V_(TM)distributions without increasing process complexity. Further, it isalways desirable to provide a DRAM cell with a capacitor havingincreased capacitance and a dielectric of increased reliability.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a floating gate fora single transistor flash EPROM cell that reduces V_(TM) distributions.

It is another object of the invention to provide a method of fabricatinga floating gate for flash EPROM cells that reduces the over-eraseproblem.

It is another object of the present invention to provide a capacitorelectrode for a DRAM cell capacitor that provides increased capacitance.

It is another object of the present invention to provide a capacitorelectrode for a DRAM cell capacitor that provides improved dielectricquality.

According to a first embodiment of the present invention an array ofsingle transistor flash EPROM cells is fabricated with each cell havinga stacked gate structure that includes a floating gate, an intergatedielectric, and a control gate. The floating gate is composed ofnitrogen in-situ doped amorphous silicon. The amorphous structure of thefloating gate eliminates the presence of relatively large grainboundaries that result in wide V_(TM) distributions.

According an aspect of the invention, the amorphous silicon is dopedresulting in a more uniform and dense distribution of "oxide valleys",and correspondingly, a more uniform distribution of V_(TM) s over thearray of cells.

According to another aspect of the present invention the intergatedielectric includes a layer of silicon dioxide formed by oxidizing thefloating gate resulting in an intergate dielectric having less inherentstress, and as a result, fewer oxide defects.

According to an alternate embodiment of the present invention a DRAMcell is fabricated with cell capacitor electrodes composed of nitrogenin-situ doped amorphous silicon. The oxidation and back-end temperaturecycles of the nitrogen in-situ doped amorphous silicon results in alower oxidation rate and low stress thermally grown silicon dioxide.Thus a DRAM cell fabricated with the improved microcrystalline structureof the amorphous silicon can have increased cell capacitance in additionto a higher quality silicon dioxides around the capacitor electrodes.

Other objects and advantages of the invention will become apparent inlight of the following description thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side cross sectional view illustrating the structure of asingle transistor flash EPROM cell according to the prior art.

FIG. 2 is a block diagram illustrating a method of manufacturing asingle transistor flash EPROM cell according to the present invention.

FIGS. 3a-3i are side cross sectional views illustrating a method ofmanufacturing a single transistor flash EPROM cell according to thepresent invention. FIGS. 3a, 3b, 3h and 3I are taken along the length ofthe transistor. FIGS. 3c-3g are taken along the width direction of thetransistor.

FIG. 4 is a side cross sectional view of three gate EPROM cell accordingto an alternate embodiment of the present invention.

FIG. 5 is a side cross sectional view of DRAM cell according to analternate embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The preferred embodiment of the present invention is an in-situ nitrogendoped amorphous silicon (α-Si) electrode employed as a floating gate ina single transistor flash EPROM cell. The preferred embodiment setsforth the single transistor cell and a method of manufacturing thereof.

FIG. 2 sets forth, in a general block diagram, the various steps forfabricating a flash EPROM cell according to a preferred embodiment ofthe present invention. A tunnel oxide is formed on the surface of ap-type silicon substrate (step 100). A layer of nitrogen doped α-Si isdeposited over the tunnel oxide (step 102) and patterned to create afloating gate (step 104). The use of nitrogen doped α-Si provides anumber of advantages over the prior art, as will be discussed at a laterpoint herein. The floating gate is oxidized to form a first layer ofsilicon oxide around the α-Si floating gate (step 106). A layer ofsilicon nitride is deposited over the first layer of silicon oxide (step108) and subsequently oxidized to create a second layer of silicon oxide(step 110). Steps 106, 108 and 110 produce a three layer dielectric ofsilicon dioxide, silicon nitride, and silicon oxide (also referred to as"ONO"). The ONO is patterned to provide protection to the sides of theα-Si gate (step 111). A layer of polycrystalline silicon (polysilicon)is then deposited over the patterned ONO (step 112).

A gate stack is formed according to the present invention usingconventional techniques. Referring once again to FIG. 2, it is shownthat a gate stack etch mask is formed on the polysilicon and a gatestack formed by a pattern gate stack step (step 114). The gate stack isoxidized in a sidewall formation step (step 116) and the processconcludes with conventional process techniques (step 118).

Referring now to FIGS. 3a-3i a number of cross sectional views are setforth illustrating a single transistor flash EPROM cell fabricatedaccording to the present invention. FIG. 3a is a side cross sectionalview taken along the channel "length" direction of the cell to beproduced. The figure illustrates the EPROM cell following the completionof step 100 and includes a substrate 200 with the tunnel oxide 202formed thereon. In the preferred embodiment the substrate is P-typesilicon and the tunnel oxide 202 is formed by thermally growing a thinlayer of silicon dioxide on the substrate. While the preferredembodiment sets forth silicon dioxide as the tunnel oxide material, thisshould not be construed as limiting the invention to a particular typeof tunnel oxide.

FIG. 3b illustrates the EPROM cell following step 102 of FIG. 2, andlike FIG. 3a is a cross sectional view along the channel lengthdirection. A layer of amorphous silicon (α-Si) 204 is deposited over thetunnel dielectric 202. The α-Si 204 has a thickness of approximately1000Å and, as is well known in the art, is micro-crystalline instructure. The α-Si 204 is nitrogen doped by an in-situ, low pressurechemical vapor deposition (LPCVD) process using disilane (Si₂ H₆) andammonia (NH₃) gases. In the preferred embodiment the conductivity of theα-Si 204 is adjusted by an ion implantation of an "n" or "p" typeimpurity.

FIG. 3c represents the EPROM cell following step 104. The α-Si 204 hasbeen patterned to create a floating gate 206. Unlike FIGS. 3a and 3b,FIG. 3c is a cross sectional view along the "width" direction of thecell which is perpendicular to the length direction. Accordingly, FIG.3c illustrates field oxide 207 created by a local oxidation of silicon(LOCOS) process. The LOCOS of the preferred embodiment is conventionaland so will not be discussed in detail herein. Conventionalphotolithographic techniques are used to create an etch mask for theα-Si 204 and anisotropic etching is used to pattern the α-Si 204 intothe floating gate 206. In the preferred embodiment reactive ion etching(RIE) is used to etch the exposed portions of the α-Si down to thetunnel oxide layer 202. RIE etch methods selective to α-Si with respectto silicon dioxide are well known in the art and so will not bediscussed in detail herein.

FIG. 3d illustrates step 106 of the process. FIG. 3d is a side crosssectional view along the width direction of the EPROM cell. Followingthe formation of a floating gate 206, the first layer of a triple layerintergate dielectric is formed by oxidizing the α-Si floating gate 206to create a first intergate dielectric layer 208 of silicon dioxide. Inthe preferred embodiment the oxidation employs ambient steam and thethickness of the first intergate dielectric is approximately 100Å. It isnoted that the nitrogen doped α-Si provides advantages over floatinggates of the prior art in that the floating gate 206 of the presentinvention retains its micro-crystalline structure throughout theoxidation step (step 106) resulting in a smooth, low stress edgemorphology on the floating gate 206. The reduction in stress reduces thechances of oxide defects from forming which are known to contribute todata retention errors.

Following the oxidation of the floating gate 206, the remainder of theintergate dielectric is formed by steps 108 and 110 of FIG. 2. Referringnow to FIG. 3e taken along the width direction of the cell, it is shownthat a thin layer of silicon nitride is deposited over the cell. Thesilicon nitride is the second dielectric layer 210. In the preferredembodiment, chemical vapor deposition is used to cream a silicon nitridelayer of approximately 100Å. FIG. 3e also shows the EPROM cell followingstep 110. The silicon nitride is oxidized to create a layer of silicondioxide which forms the third intergate dielectric layer 212. In thepreferred embodiment the resulting thickness of the third intergatedielectric is in the range of 30Å. The result is an ONO layer over thefloating gate 206.

FIG. 3f is a side cross sectional view taken along the width directionof the EPROM cell following step 111. The ONO is patterned and etched toprovide an ONO pattern 211 that protects the sides of the floating gate206.

A polysilicon layer 214 is deposited over the ONO pattern 211 in step112. FIG. 3g, taken along the width direction of the cell, illustratesthe polysilicon layer 214 following deposition. The polycrystallinestructure is fancifully illustrated to distinguish it from themicro-crystalline structure of the floating gate 206. In the preferredembodiment the polysilicon is doped to increase conductivity andincludes a top layer of silicide. The deposition of the polysilicon andthe formation of the silicide are well known in the art and so will notbe discussed any further detail herein.

The entire structure set forth in FIG. 3g is patterned by a pattern gatestack step (step 114). The EPROM cell following this step is illustratedin FIG. 3h. Unlike FIGS. 3c-3g, FIG. 3h is taken along the lengthdirection of the cell. Using conventional photolithographic techniques,an etch mask for a gate stack is formed and an anisotropic etch applied.The unmasked areas are etched down to the tunnel dielectric 202. Theetch mask is stripped leaving a gate stack 216, as is shown in FIG. 3h.The gate stack 216 includes a control gate 218 patterned from thepolysilicon layer 214, and the three intergate dielectric layers (208,210 and 212) intermediate the floating gate 206. FIG. 3h also fancifullyillustrates a source-drain implant step wherein an n+source and drainare created. As is well understood in 1-T EPROM cell configurations,during erase operations, a diffusion region receives electrons from thefloating gate via tunneling. Accordingly, in the preferred embodiment,the erase electrode is the source diffusion.

The formation of gate stack sidewalls 220 and the subsequent "back end"process of steps 116 and 118 of FIG. 2 are represented by FIG. 3i, takenalong the length direction. As shown in FIG. 3i, the gate stack 216 issubject to additional oxidation steps to form the sidewalls 220. Thein-situ nitrogen doping of the floating gate 206 provides furtheradvantages for the EPROM cell of the present invention. Due to thenitrogen doping, the α-Si maintains a microcrystalline structurethroughout the "back end" (steps 116 and 118) of the fabricationprocess. As a result, the side wall oxidation of the floating gate 206produces a lower stress oxide. This reduces the occurrence of sidewalloxide defects which create data retention errors due to charge leakagethrough the defects. Further, the nitrogen doped α-Si can undergo alarger number of back-end temperature cycles and/or higher back-endprocess temperatures than conventional α-Si before adversely largecrystalline grain structures (and consequently oxide valleys) arecreated. Accordingly, the present invention provides more back-endtemperature flexibility in addition to better V_(TM) distributions.

While the preferred embodiment sets forth a single transistor flashEPROM cell and method of manufacturing thereof, it is understood thatthe invention is applicable to any device utilizing Fowler-Nordheimtunneling to transfer electrons from a floating gate through a runneldielectric. Just a few examples would be flash EPROM cells of "step"gate or three gate design, or even "conventional"EEPROMs. An alternateembodiment employing the three gate design is set forth in FIG. 4. Theembodiment is designated by the general reference character 250 andincludes a floating gate 252 formed from nitrogen doped amorphoussilicon, a control gate 254, and an erase gate 256. The operation of thethree gate alternate embodiment is conventional in nature.

An alternate embodiment of the present invention is illustrated in FIG.5. The alternate embodiment employs two in-sire nitrogen doped amorphoussilicon electrodes as a first and second capacitor plate in singletransistor DRAM cell capacitor. FIG. 5 sets forth a single transistorDRAM cell 300 that includes a cell capacitor 302. The cell capacitorincludes a first capacitor plate 304 and a second capacitor plate 306.Both capacitor plates (304 and 306) are fabricated in a similar manneras the floating gate described in the above EPROM cell.

Intermediate the capacitor plates (304 and 306) is a capacitordielectric 308. The alternate embodiment uses a layer of silicon nitride310. One skilled in the art would recognize that the nitride isdeposited over the first capacitor plate 304 prior to the deposition andpatterning steps that create the second capacitor plate 306. Furtherreference to FIG. 5 illustrates a first silicon dioxide layer 312 and asecond silicon dioxide layer 314. As is well known in the art theselayers are very thin when initially formed but can grow duringsubsequent fabrication steps. Unlike the prior art, the nitrogen dopedα-Si oxidizes at a much slower rate than polysilicon or undoped α-Si.Accordingly, the silicon dioxide layers (312 and 314) of the capacitordielectric 308 are much thinner than those of the prior art. Thisresults in greater capacitance in the DRAM cell 300. As will be recalledfrom above, the oxide formed possesses less inherent stress, and so hasfewer defects. It is noted that the microcrystalline structure of thenitrogen doped α-Si creates additional capacitor area, and if thecapacitor plates (304 or 306) are doped, results in less oxide valleysas described in the prior art, increasing the reliability of the siliconoxide layer.

As will be apparent to one skilled in the art, the invention has beendescribed in connection with its preferred embodiments, and may bechanged, and other embodiments derived, without departing from thespirit and scope of the invention.

What I claim is:
 1. A monolithic semiconductor device having a floatinggate that uses electron tunneling to transfer electrons from thefloating gate through a tunnel dielectric to an erase electrode,comprising:a control gate; an erase electrode; a floating gate formed ofnitrogen doped amorphous silicon; a tunnel dielectric intermediate saiderase electrode and said floating gate; and an intergate dielectricintermediate said control gate and said floating gate.
 2. Thesemiconductor device of claim 1 wherein:the nitrogen doped amorphoussilicon is in-situ nitrogen doped amorphous silicon.
 3. Thesemiconductor device of claim 1 wherein:said floating gate is doped withan N-type dopant.
 4. The semiconductor device of claim 1 wherein:saidfloating gate is doped with a P-type dopant.
 5. The semiconductor deviceof claim 1 wherein:the semiconductor device is a three gate EPROM cell;and said erase electrode is an erase gate formed from a depositedconductive layer.
 6. The semiconductor device of claim 1 wherein:saiderase electrode includes at least one doped region in a substrate. 7.The semiconductor device of claim 6 wherein:said control gate, saidfloating gate, said intergate dielectric, and said erase electrode arepans of a single memory cell.
 8. The semiconductor device of claim 7wherein:the said single memory cell is of stacked gate design, saidfloating gate being disposed over the substrate with said tunneldielectric therebetween, the control gate being disposed over thefloating gate with the intergate dielectric therebetween, and the eraseelectrode is a source region in the substrate.
 9. The semiconductordevice of claim 1 wherein:at least a portion of the total thickness ofthe intergate dielectric is silicon dioxide thermally grown on saidfloating gate.
 10. In a semiconductor integrated circuit, a capacitorfor storing charge comprising:a first electrode formed of a layer ofnitrogen doped amorphous silicon; a second electrode; and a capacitordielectric including at least one layer of silicon dioxide formed by theoxidation of the first electrode.
 11. The capacitor of claim 10wherein:said second electrode is formed of a layer of deposited nitrogendoped amorphous silicon.
 12. The capacitor of claim 10 wherein:saidcapacitor dielectric includes a second layer of deposited siliconnitride.
 13. The capacitor of claim 12 wherein:said capacitor dielectricincludes a third layer of silicon dioxide formed by the oxidation of thesecond dielectric layer.